1. Field of the Invention
The present invention relates to a motion amount detection apparatus for detecting amounts of relative motion between the pictures expressed by successive fields of a video signal, such as motion resulting from camera shake in the case of a video signal produced from a compact type of video camera.
2. Description of the Related Art
FIG. 1 is a general block diagram of an example of a prior art motion amount detection apparatus, which is described in Japanese Patent laid-open No. 1-269371. Four positions, referred to as representative points, are fixedly defined by the apparatus in a specific horizontal line interval of each field of an input video signal, respectively corresponding to four picture elements of the video signal. Such a set of four representative points are illustrated in FIG. 2, designated as P0, P1, P2 and P3. These occur in the horizontal line interval with a fixed spacing of 17 picture element intervals between successive representative points, as shown.
In FIG. 1, numeral 1 denotes a source of a digital video signal, 2 denotes a representative point memory circuit for storing signal values of representative points within the video signal, and 3 denotes a memory control circuit I for controlling the representative point memory circuit 2. 4 denotes an operational circuit for operating on the signal which is read out from the representative point memory circuit 2, which constitutes representative point values from a field occurring one field or more previously, and on the output signal from the digital video signal source 1, which constitutes the current video signal. 5 denotes a detection memory circuit which is formed of a plurality of memory circuit section, for storing output signal values from the operational circuit 4. 6 denotes a memory control circuit II for controlling the detection memory circuit 5. 7 denotes a motion amount operational circuit for periodically obtaining an amount and direction of image motion based on the cumulative stored contents in the detection memory circuit 5, e.g once in each field interval. 8 denotes a representative point specifying circuit for determining the positions (within each field interval) of the representative points P0, P1, P2, P3 for which picture element Values are stored in the representative point memory circuit 2. 9 denotes an operation control circuit for controlling the representative point specifying circuit 8 and the memory control circuit 6. 10 denotes a system control circuit, for providing overall control of the aforementioned circuits.
The operation of the above circuits is as follows. A digital video signal is inputted from the digital video signal source 1, and picture element values corresponding to the representative point positions designated by the representative point specifying circuit 8 are written into the representative point memory circuit 2 under the control of the memory control circuit 3. The values which are thus written in are outputted in during respective predetermined time intervals (referred to in the following as comparison intervals) in the succeeding frame, i.e. during the current field of the video signal the representative point values for the preceding field are outputted during respective comparison intervals. The operational circuit 4 operates on the current video signal and the representative point video signal values of the preceding frame to obtain operational result values which can be subsequently used to judge an amount of picture motion, specifically by subtracting from successive picture element values of the current field, FIG. 2, these comparison intervals successively overlap. Thus, (although not apparent from the simple block diagram of FIG. 1), pairs of result values will be outputted in parallel from the operational circuit 4 within the regions of overlap between these ranges. For example, assuming that the n.sup.th picture element of the horizontal line interval containing the representative points corresponds to representative point P0, then the n.sup.th picture element of the current field will be compared (in the operational circuit 4) with the P0 representative point value from the preceding field at the position R032 within the comparison interval .vertline.R0.vertline., while at the same time being compared with the P1 representative point value from the preceding field at the position R115 within the comparison interval .vertline.R1.vertline..
The basic principles of the apparatus are as follows. Each result that is obtained for a specific representative point value within a comparison interval is cumulatively added to each of the results obtained for the same relative position within each of the other three comparison intervals. Thus for example the four results obtained for the four representative points P0, P1, P2, P3 which have the relative positions R032, R132, R232 and R332 respectively, are cumulatively added and stored in one specific address of one specific memory during each comparison interval, the representative point value (from the preceding field) corresponding to that comparison interval, obtaining the absolute value of each subtraction and operating on that absolute value to obtain an operational result. These result values are cumulatively written into respectively selected ones of the memory circuit section of the detection memory circuit 5, under the control of the memory control circuit 6. In the first embodiment of that invention, there are four comparison intervals respectively corresponding to four representative points. Two of the respective ranges of these comparison intervals are illustrated in FIG. 2, designated as .vertline.R0.vertline. and .vertline.R1.vertline. respectively. As shown, each comparison interval is equal to 64 picture element intervals, i.e. four times the spacing between adjacent representative points. Positions within each comparison interval with respect to the representative point of that interval are expressed by respective sets of designations, two of which these sets, R00 to R064, and R10 to R164 being shown in FIG. 2, i.e. each set consists of 64 picture element positions. In the following, the distance between such a position within a comparison interval and the corresponding representative point will be designated as a relative distance value. As shown in circuit section of the detection memory circuit 5. FIG. 3 illustrates how the results obtained for the various relative positions R00 etc. are stored in respective addresses and memory circuit sections of the detection memory circuit 5. Upon completion of such a cumulative addition and storage operation for the four successive representative points, if for example there has been no relative movement of the picture expressed by the current field with respect to the preceding field, then the final cumulative result obtained for the four representative point positions (which is stored in address 8 of the memory circuit section MO as shown in FIG. 3), will be the smallest of all of the cumulative results that are left stored in the addresses of each of the memory circuit sections M0, M1, M2 and M3. Hence, the motion amount detection circuit 7 will judge in this case that there has been no picture motion, based on the contents left stored in the detection memory circuit 5.
Conversely if there has been some relative picture motion (in the horizontal direction, in this example), then the smallest value of cumulative result will be left in some other address of one of the memory circuit section M0 or of M1, M2 or M3. The amount and direction of the motion can be judged by the motion amount detection circuit 7 based on the memory location of that minimum cumulative result.
With that prior art apparatus, it is necessary to provide a set of n memory circuit sections, where n is a natural number, and the spacing between two successive representative points is set as (n.N +1), where N is a natural number representing the number of memory circuit sections and n is a coefficient. n and N are each equal to 4 in the prior art example being described. To determine the memory circuit section to which an operational result value is to be written, the distance between the relative position for that result and the corresponding representative point is divided by N, and the value of the remainder determines the memory circuit section into which the result is to be written. For example, the distance between the relative position R00 (in the comparison interval .vertline.R0.vertline.) and the corresponding representative point P0 is equal to 32. The remainder from dividing 32 by 4 is zero, so that each result obtained for the relative position R00 will be written into the memory circuit section M0.
However with such an apparatus, various practical problems arise. Firstly, successively adjacent result values must be written into successively different ones of the memory circuit sections. For example, results obtained for the relative positions R00, R01, R02 and R03 must be written into the memory circuit sections M0, M3, M2 and M1 respectively, as shown in FIG. 3, although these result values are obtained in continous succession by the operational circuit 4. This is due to the fact that of course respectively different values of division remainder will be obtained for successive relative positions, within each of the comparison intervals .vertline.R0.vertline. to .vertline.R3.vertline..
Furthermore, when two result values are obtained in parallel for two different comparison intervals (for example, values obtained for the positions R032 and R115 each based on comparison with the n.sup.th picture element of the current field as illustrated in FIG. 2), these two values must be written into respectively different addresses. Thus, memory control for the motion amount detection circuit 7 is complex, and so the memory control circuit scale must be large.
A second basic problem which arises with prior art types of motion amount detection apparatus is that it has been difficult to reduce the number of bits used for the digital signals that are processed by the apparatus. It is desirable to use only a small number of bits to express each digital value, in order to minimize the circuit scale, i.e. a smaller number of bits than is required to express the full dynamic range of the input digital video signal. To achieve that objective, it has been proposed in the prior art (for example in Japanese Patent laid-open No. 2-241188) to operate on the input digital video signal of such an apparatus by removing high-order bits from of each digital value of the input signal. However the problem of overflow between corresponding picture element values of successive fields will arise with such a method. For example, assuming for simplicity that each picture element value of the input digital video signal is expressed by 8 bits and that a representative point has the binary value "0 0 0 0 1 1 1 1" in one field, i.e. the MSB is 0 and the LSB is 1, and has the value "0 0 0 1 0 0 0 0" in the succeeding field, then if the high-order three bits are removed, no error will result when the remaining two sets of low-order bits are compared. However if the four high-order bits are removed, then a comparison error will occur, i.e. the values "1 1 1 1" and "0 0 0 0" will be compared. Thus if such a simple removal method is utilized and a large reduction in the number of bits is achieved, then there may be errors in the absolute values that are obtained from comparisons of the representative point values.